China’s semiconductor industry is racing to catch up to the West, but The Economist’s key point lands like a weight on the dashboard: it is proving easier to design chips than to make them. That single sentence explains why the industry’s progress can look fast on paper and stubborn in the real world. Designers can iterate quickly. Factories cannot. And when the goal is “catch the West,” the gap is rarely in imagination. It is in manufacturing.

On the design side, the work is largely about mastering complexity: architectures, instruction sets, toolchains, and optimization. In semiconductor terms, you can often move from concept to prototype with relatively shorter feedback loops. The Economist is essentially telling us that China can push that part forward. The problem shows up when you switch from “can we design this?” to “can we manufacture it reliably, cheaply enough, and at the required scale?” That is the bottleneck that keeps the West out in front, even as the sprint in design continues.

To understand why this matters, you have to know how semiconductors actually get built. Cutting edge chips rely on extremely precise processes, advanced equipment, controlled environments, and yields that only improve with time and learning. Manufacturing is a cumulative discipline. Even a great design can stall if the process steps do not reliably produce working chips. And yields matter because they determine cost. A lab demo is one thing. A production line that ships to customers consistently is another. When The Economist says it is easier to design chips than to make them, it is pointing to that asymmetry: the skills and capex behind chipmaking are harder, slower, and more constrained than the skills behind chip design.

Now add the geopolitical and regulatory layer that sits over the industry like a ceiling. Semiconductors are not treated like ordinary hardware. Supply chains are strategic. Export controls, licensing regimes, and restrictions on certain kinds of equipment and technology shape what companies can buy and where. Even when governments want domestic capacity, those rules can turn manufacturing upgrades into multi-year projects with uncertain access. Decision-makers therefore face a planning reality that looks less like a normal tech roadmap and more like a risk-management exercise: where can we access what we need, how quickly can we ramp, and what happens if inputs remain constrained.

This is also why “race to catch up” can be a confusing phrase for boards and investors. Races imply a roughly linear path. Semiconductors do not behave linearly. There is progress in design, but manufacturing progress is tied to physical realities and supply constraints. So the industry can post encouraging development updates while customers still wait for scalable output. That mismatch can create internal pressure. It can also create the wrong focus. If you track only design milestones, you can mistakenly believe the race is ahead of schedule. If you track only production output, you can miss that the design pipeline is building something potentially important. The winning approach is to measure both, but with a clear hierarchy that respects manufacturing bottlenecks.

Second-order implications follow quickly. When manufacturing is the limiting factor, capital allocation becomes more sensitive to execution, not just ambition. Money spent on design talent might pay off sooner, but it will not substitute for missing manufacturing capability. Likewise, investments in factories are not only about building capacity. They are about learning curves, defect reduction, yield optimization, and supply chain integration. The board-level challenge is to distinguish between “we are building capability” and “we are producing at scale.” Those are different timelines, different indicators, and different risk profiles.

For peer executives, the takeaway is blunt. If you are a founder, CFO, or investor evaluating semiconductor strategies, you cannot treat design wins as proof of commercial readiness. The Economist’s framing implies that the West’s advantage is tied to manufacturing depth, not just design sophistication. That means peers need to think harder about partnerships, equipment access, process development timelines, and how quickly production can be ramped once the design is ready. In a race where manufacturing is the throttle, the stopwatch starts ticking only when the fab can deliver.