IBM’s nanostack prototype packs 100B transistors per fingernail, aiming to extend Moore’s Law

IBM has built a prototype chip with around 100 billion transistors on an area the size of a fingernail. That density is twice the company’s previous state-of-the-art technology announced in 2021, and the design is explicitly meant to keep Moore’s Law moving even as shrinking transistors runs into quantum limits.

The “how” is the real story: IBM’s new nanostack architecture vertically stacks transistors in two layers on a silicon chip. Compared with IBM’s prior state-of-the-art architecture, IBM reports chips built with this approach can do as much as 50% more work in the same amount of time and be up to 70% more energy efficient. In plain terms, IBM is trying to squeeze more computing out of the same clock cycles and cut the electricity bill at the same time, which is exactly what operators at data centers and power-constrained computing environments have been asking for.

For more than half a century, chipmakers followed Moore’s Law by cramming more transistors onto a chip, mostly by shrinking them. But in the last 15 years, transistors have gotten close to where quantum mechanics starts to interfere with their function, just a few dozen nanometers in size. The industry hit a wall on “make it smaller,” so the industry pivoted toward an approach that sounds like something an urban planner would understand: build up. Instead of reducing transistor size further, IBM stacks layers vertically so more transistors can fit in the same footprint.

IBM says its solution is a nanostack made with a complementary field-effect transistor, or CFET, style architecture. As described, the company fabricates transistors on one silicon layer, places another silicon layer on top, fabricates a second layer of transistors directly on top of that, then creates the electrical connections between the two layers. Jay Gambetta, director of IBM Research, called it “not just an incremental step” but “a meaningful leap forward,” and he expects that within a decade, chips with nanostacking will be widely used in data centers, where efficiency improvements could help facilities better manage energy consumption.

That “energy consumption” part is not a throwaway. Data centers are already operating under tight constraints: power availability, heat removal, and operational costs all influence how quickly new capacity can come online. When an architecture can be “up to 70% more energy efficient” while delivering “as much as 50% more work” in the same time, it changes the economics, not just the benchmarks. Dan Hutcheson, vice chair at TechInsights, went further, saying the work “puts another 10, 15 years on the roadmap.” For executives, that kind of runway matters because it influences capital planning, procurement cycles, and the urgency of platform redesigns.

The practical question is whether IBM’s approach can be manufactured at scale without turning yield into a nightmare. A professor of materials science and engineering at the University of Illinois at Urbana-Champaign, Qing Cao, who was not involved with the work, flagged two major challenges when moving to stacked layers. First, errors introduced during manufacturing mean a certain number of chips are faulty upon creation; with a stacked design, if either the top layer or the bottom layer fails, the entire chip fails, increasing the failure rate and therefore the cost. Second, there is the “thermal budget”: engineers must build each layer without melting connections to the one underneath, which means keeping manufacturing processes below 400 °C. IBM says it figured out how to make the second stack at low enough temperature, though the company is mum about its methods.

IBM’s architecture also has a differentiation claim that matters for performance and manufacturability: in IBM’s design, transistors in the second layer do not sit directly on top of the first layer’s transistors. Instead, they are staggered, which IBM says simplifies wiring among other advantages. That distinction places IBM’s nanostack in the broader CFET ecosystem being pursued by other major players, including Intel, Samsung, TSMC, and the competing research lab Imec in Belgium.

It is also not the only “two-tier” path in play. Cao contrasted nanostacking with other approaches such as AMD’s 3D V-Cache and Huawei’s forthcoming LogicFolding, where engineers fabricate transistors on each layer independently before bonding the two together. Cao said IBM’s method allows more precise alignment of the layers, which is important because transistors are so tiny. Alignment precision, in chip terms, is a performance story. In operational terms, it is also a reliability story, because small misalignments can ripple through timing, power draw, and system-level stability.

Looking under the hood, IBM’s nanostack builds on nanosheet technology used for state-of-the-art transistors since around 2022. A transistor acts like a hose through which electrons flow, controlled by a valve to turn the flow on or off. In IBM’s nanostack approach, the channel consists of three nanosheets, each 15 atoms thick and spaced nine nanometers apart. IBM refers to its nanostack technology as “sub-nanometer” or “0.7 nanometer,” using a longtime industry convention where each generation is named for a smaller and smaller length. But “0.7 nanometer” is a marketing term and does not correspond to any physical characteristics of the chip.

So what’s next? IBM says the architecture offers a general way of laying out transistors and plans to partner with semiconductor manufacturers to make the actual chips. It anticipates chip designers will deploy the design in many different types of chips, including GPUs and CPUs. Meanwhile, academics are exploring alternative stacking strategies. Cao’s group created a method for stacking transistors layer by layer where the second layer is created with processes below 200 °C, using junctionless transistors created without the typically required step called doping, which injects non-silicon atoms into silicon and is usually the hottest part of fabrication. Cao thinks stacking techniques could be easier to scale up to multiple tiers from a thermal management perspective, but his demonstration is described as a proof of principle.

If this IBM nanostack prototype can transition from a “full wafer using a state-of-the-art manufacturing line” to high-yield production, it does more than extend a timeline. It potentially reshapes the playbook for how chips evolve when shrinking hits physics. And because IBM is explicitly pitching data centers as the early mass market for nanostacking, it also puts pressure on rival roadmap planning. If you are an executive allocating budgets across compute platforms, the question becomes less “who has the better lab demo” and more “which architectures will actually survive the thermal budget, yield curve, and energy reality of the real world.”